g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 1 - features : description : * low-power consumption. - active: 30ma at 55ns. -stand by : 5 m a (cmos input / output) 1 m a (cmos input / output, sl) * single +2.7 to 3.3v power supply. * equal access and cycle time. * 55/70/85/100 ns access time. * easy memory expansion with ce1 , ce2 and oe inputs. * 2.0v data retention mode. * ttl compatible, tri-state input/output. * automatic power-down when deselected. the glt6100l08 is a low power cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low ce1 , an active high ce2, an active low oe, and tri- state i/o?s. this device has an automatic power- down mode feature when deselected. writing to the device is accomplished by taking chip enable 1 ( ce1 ) with write enable ( we ) low, and chip enable 2 (ce2) high. reading from the device is performed by taking chip enable 1 ( ce1 ) with output enable ( oe ) low while write enable ( we ) and chip enable 2 (ce2) is high. the i/o pins are placed in a high-impedance state when the device is deselected : the outputs are disabled during a write cycle. the glt6100l08 comes with a 2v data retention feature and lower standby power. the glt6100l08 is available in a 32-pin tsopi / stsop / 48-fpbga packages. pin configurations : glt6100l08 a 16 a 7 1 2 3 4 5 6 8 9 10 11 12 13 22 21 19 18 17 26 25 24 23 gnd oe a 10 14 27 28 i/o 8 i/o 7 20 a 0 7 we v cc nc 15 16 29 30 31 32 a 11 a 9 a 8 a 13 ce 2 a 15 a 14 a 12 a 6 a 5 a 4 a 3 a 2 a1 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 ce 1 function block diagram : row decoder 1024 x 1024 sense amp input buffer column decoder a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 control circuit oe we ce1 ce2 i/o 8 i/o 1
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 2 - pin descriptions: name function a - a 0 16 address inputs ce 1 and ce 2 chip enable input oe output enable input we write enable input i o i o 0 7 / / - data input and data output v cc 3v power supply gnd ground nc no connection truth table: ce 1 ce 2 we oe data mode h x x x high-z standby x l x x high-z standby l h h l data out active, read l h h h high-z active, output disable l h l x data out active, write absolute maximum ratings* parameter symbol minimum maximum unit voltage on any pin relative to gnd vt -0.5 4.6 v power dissipation p t - 1.0 w storage temperature (plastic) tstg -55 +150 c temperature under bias tbias -40 +85 c *note : stresses greater than those listed above absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions ( ta = -25 c to 85 c )** parameter symbol min typ max unit supply voltage v cc 2.7 3.0 3.3 v v ih 2.2 - v cc +0.5 v input voltage v il -0.5* - 0.6 v * v il min = -1.0v for pulse width less than t rc /2. ** for industrial temperature.
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 3 - dc operating characteristics ( vcc=2.7v to 3.3v, t a =-25 c to 85 c ) 55 70 85 100 parameter sym. test conditions min max min max min max min max unit input leakage current ? i li ? v cc = max, vin = gnd to v cc 1 1 1 1 m a output leakage current ? i lo ? ce 1 =v ih or ce2 = v ih v cc = max, v out = gnd to v cc 1 1 1 1 m a operating power supply current i cc ce 1 =v il ,ce2 = v ih v in =v ih or v il , i out =0ma 3 3 3 3 ma i cc1 ce 1 =v il ,ce2 = v ih i out = 0ma, min cycle, 100% duty 30 25 20 15 ma average operating current i cc2 ce 1 =0.2v ce2 = v cc ? 0.2v i out = 0ma, cycle time=1 m s, 100% duty 3 3 3 3 ma standby power supply current(ttl level) i sb ce 1 =v ih or ce2 = v il 0.5 0.5 0.5 0.5 ma glt6100l08ll 5 5 5 5 m a standby power supply current (cmos level) i sb1 ce 1 3 v cc - 0.2v or ce2 0.2v, f=0 v in 0.2v or v in 3 v cc -0.2v glt6100l08sl 1 1 1 1 m a output low voltage v ol i ol = 2 ma 0.4 0.4 0.4 0.4 v output high voltage v oh i oh = 2 ma 2.4 2.4 2.4 2.4 v data retention parameter sym. test conditions min. max. unit v cc for data retention v dr 1.0 - v data retention current i ccdr 5 m a chip deselect to data retention time t cdr 0 - ns operating recovery time (2) t r ce 1 3 v cc -0.2v or ce 2 +0.2v, v in 3 v cc -0.2v or v in 0.2v t rc - ns
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 4 - data retention waveform (ta = -25 c to 85 c) data retention mode vcc ce v dr v dr >= 1.0v t r t cdr 2.7v 2.7v v ih v ih ac test conditions ac test loads and waveforms c l * ttl output load condition *including scope and jig capacitance 70ns / 85ns c l = 30pf + 1ttl load load 100ns / 120ns c l = 100pf + 1ttl load read cycle (3,9) ( vcc=2.7v to 3.3v, t a =-25 c to 85 c ) 55 70 85 100 parameter symbol min max min max min max min max unit note read cycle time t rc 55 70 85 100 ns address access time t aa 55 70 85 100 ns chip enable access time t ace 55 70 85 100 ns output enable access time t oe 35 40 40 50 ns output hold from address change t oh 10 10 10 10 ns chip enable to output in low-z t clz 10 10 10 10 ns 4,5 chip disable to output in high-z t chz 25 30 35 40 ns 3,4,5 output enable to output in low-z t olz 5 5 5 5 ns output disable to output in high-z t ohz 25 25 30 35 ns 4,5 power-up time t pu 0 0 0 0 ns 3,4,5 power-down time t pd 55 70 85 100 ns input pulse levels 0.6v to 2.2v input rise and fall time input and output timing reference level 5 ns 1.4v
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 5 - timing waveform of read cycle 1 (3,6,7,9) (address controlled) d out t aa t oh t rc data valid address timing waveform of read cycle 2 (5,6,8,9) ( ce1 controlled) t oe t rc data valid ce1 t ohz t chz t pd 50% 50% t olz t ace t clz t pu supply current oe d out i cc i sb timing waveform of read cycle 1 (3,6,8,9) (ce2 controlled) t oe t rc data valid ce2 t ohz t chz t pd 50% 50% t olz t ace t clz t pu supply current oe d out i cc i sb
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 6 - write cycle (3,9) ( vcc=2.7v to 3.3v, t a = -25 c to 85 c ) 55 70 85 100 parameter symbol min max min max min max min max unit note write cycle time t wc 55 70 85 100 ns chip enable to write end t cw 45 60 70 80 ns address setup to write end t aw 45 60 70 80 ns address setup time t as 0 0 0 0 ns write pulse width t wp 45 50 60 70 ns write recovering time t wr 0 0 0 0 ns data valid to write end t dw 25 30 35 40 ns data hold time t dh 0 0 0 0 ns write enable to output in high-z t wz 25 30 35 40 ns output active from write end t ow 5 5 5 5 ns timing waveform of write cycle 1 (10,11) ( we controlled) t wp t aw we t wc t wr t as t dw t dh t ow t wz data valid address d in d out
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 7 - timing waveform of write cycle 2 (10,11) ( ce1 controlled) t aw we t wc t wr t dw t dh data valid address d in t as t cw t wp t wz ce1 d out timing waveform of write cycle 1 (10,11) (ce2 controlled) t aw we t wc t wr t dw t dh data valid address d in t as t cw t wp t wz ce2 d out
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 8 - notes : 1. l-version includes this feature. 2. this parameter is samples and not 100% tested. 3. for test conditions, see ac test condition. 4. this parameter is tested with cl = 5pf. transition is measured 500mv from steady ? state voltage. 5. this parameter is guaranteed, but is not tested. 6. we is high for read cycle. 7. ce1 and oe are low and ce2 is high for read cycle. 8. address valid prior to or coincident with ce1 transition low or ce2 transition high. 9. all read cycle timings are referenced from the last valid address to the first transtion address. 10. ce1 or we must be high or ce2 must be low during address transition. 11. all write cycle timings are referenced from the last valid address to the first transition address.
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 9 - ordering information part number speed power package glt6100l08ll-55ts 55ns normal tsopi 32l glt6100l08ll-70ts 70ns normal tsopi 32l glt6100l08ll-85ts 85ns normal tsopi 32l glt6100l08ll-100ts 100ns normal tsopi 32l glt6100l08ll-55st 55ns normal stsopi 32l glt6100l08ll-70 st 70ns normal stsopi 32l glt6100l08ll-85 st 85ns normal stsopi 32l glt6100l08ll-100 st 100ns normal stsopi 32l glt6100l08sl-55ts 55ns normal tsopi 32l glt6100l08sl-70ts 70ns normal tsopi 32l glt6100l08sl-85ts 85ns normal tsopi 32l glt6100l08sl-100ts 100ns normal tsopi 32l glt6100l08sl-55st 55ns normal stsopi 32l glt6100l08sl-70 st 70ns normal stsopi 32l glt6100l08sl-85 st 85ns normal stsopi 32l glt6100l08sl-100 st 100ns normal stsopi 32l parts numbers (top mark) definition : glt 6 100 l 08 ll- 55 ts note : c cdrom , h hdd. example : 1.glt710008- 15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016- 40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 64k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) *see note voltage blank : 5v l : 3.3v m : 2.5v n : 2.1v config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) st : stsop (type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp ll : low low power l : low power : standard sl : super low power
g-link glt6100l08 ultra low power 128k x 8 cmos sram nov 2000(rev. 02) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 10 - package information 32 pin 8x20mm small outline j-form package (tsop) 32 pin 8x13.4mm small outline j-form package ( stsop)
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